A half adder circuit performs a 1-bit binary addition, producing a Sum output and also a Carry-Out to a more significant stage. Operation of the half adder is summarised in the following truth table.
The half adder may be constructed using an XOR (exclusive-or) gate, plus an AND gate, as shown below.
A shortcoming of this circuit is the inability to accept a Carry-In from a previous stage. This problem is overcome in the full adder circuit.